1. Technical Field
The present invention relates to wafer bonding, and more particularly to methods for improving alignment between wafers to be bonded.
2. Description of the Related Art
Bonding layer grid mismatch between top and bottom wafers can be observed prior to wafer bonding. Mismatches between these layers increase limitations to scaling through silicon vias (TSVs) and associated TSV landing pad areas. Such differences can occur during lithographic processing or, more likely, due to bonding preparation, especially if the wafers are quite different (e.g., single versus stack, pattern loading, etc.).